1. Field of the Invention
Generally, the present invention relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of improved fabrication and height control of structures used in integrated circuit devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Device designers have been very successful in improving the electrical performance capabilities of transistor devices, primarily by reducing the size of or “scaling” various components of the transistor, such as the gate length of the transistors. As size is reduced, the control of the height of fin structures on bulk substrates is difficult. Furthermore, existing methods make a CMOS flow difficult when attempting to use alternative channel materials for nFET and pFET. Conventional finFET fin formation utilizes a hard-mask and etching to etch away surrounding area, creating the fin. The trenches on each side of the fin are then filled with oxide, and excess oxide is removed with chemical mechanical planarization (CMP) and/or oxide etching. This can lead to non-uniform fin height. Also, the fins are sometimes clad with epitaxially grown silicon/germanium (SiGe) or germanium (Ge) to enhance nFET and pFET performance, respectively. Critical dimension (CD) and profile matching is difficult for differing nFET and pFET channel materials with separate etching. Common etching may not be possible for potential channel materials of silicon (Si) or group III-V semiconductor materials for nFET, and SiGE or Ge for pFET.
The present disclosure is directed to various methods of fabricating features in an integrated circuit structure, using an improved fin height control technique. These techniques can be used in CMOS circuits with alternative channel materials or traditional materials.